Semiconductor device having aerial wiring and manufacturing method thereof

ABSTRACT

A semiconductor device includes a first aerial wiring including a first wiring layer which is formed in an air gap and contains Cu as a main component and a via layer which is electrically connected to the first wiring layer, is formed in an inter-level insulating film containing a preset constituent element and contains Cu as a main component, and a first porous film formed on the first aerial wiring. The semiconductor device further includes a first barrier film which is formed to cover the surface of the first aerial wiring and contains a compound of the preset constituent element and a preset metal element as a main component.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-232387, filed Aug. 10, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention This invention relates to a semiconductordevice and a manufacturing method thereof and is applied to a multilayerwiring using an air gap structure, for example.

2. Description of the Related Art

Conventionally, a multilayer wiring using an air gap structure isproposed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No.H9-237831). The air gap structure is a structure in which a materialused to isolate adjacent wirings from each other is not a solid materialrepresented by a silicon oxide film but a gaseous material such as air.

A conventional general manufacturing method of a multilayer wiring usingthe air gap structure is as follows.

First, a wiring structure is temporarily formed in an insulating film.At this time, it is general to use a carbon film or resist as a materialof the insulating film. Further, it is general to form a barrier filmfor prevention of diffusion by use of a metal material such as Ta(tantalum) or TaN (tantalum nitride) before forming a wiring layercontaining metal such as Cu (copper) or Al (aluminum) as a maincomponent.

Then, a porous film is formed on the above wiring structure. Next, airgaps are formed by etching portions of the insulating film betweenwiring layers through the porous film by using O₂ as etching gas.

However, since an oxide gas such as O₂ is used in the above etchingprocess, the barrier film tends to be oxidized and corroded and thewiring also tends to be oxidized and corroded. This is because thebarrier film and wiring are formed of a metal material, exhibit almostno oxidation resistance and are easily oxidized and corroded by anoxidation gas such as O₂. Particularly, when the wiring structure isformed by using Cu as a main component, the above tendency becomessignificant since the Cu itself does not have oxidation resistance.

BRIEF SUMMARY OF THE INVENTION

A semiconductor device according to a first aspect of the presentinvention comprises a first aerial wiring which includes a first wiringlayer formed in an air gap and containing Cu as a main component and avia layer electrically connected to the first wiring layer, formed in aninter-level insulating film containing a preset constituent element andcontaining Cu as a main component; a first porous film formed on thefirst aerial wiring; and a first barrier film formed to cover thesurface of the first aerial wiring and containing a compound of thepreset constituent element and a preset metal element as a maincomponent.

A semiconductor device according to a second aspect of the presentinvention comprises a first aerial wiring which includes a first wiringlayer formed in an air gap and containing Cu as a main component and avia layer electrically connected to the first wiring layer, formed inthe air gap and containing Cu as a main component; a first porous filmformed on the first aerial wiring; and a first barrier film formed tocover the surface of the first aerial wiring and containing a compoundof a preset constituent element and a preset metal element as a maincomponent.

A method of manufacturing a semiconductor device according to a thirdaspect of the present invention comprises forming grooves for wirings inan insulating film; embedding an alloy film including a preset metalelement and containing Cu as a main component into the grooves; forminga porous film containing at least Si on the alloy film and insulatingfilm; and forming an air gap by removing a portion of the insulatingfilm by performing heat treatment together with an etching process in anatmosphere containing at least O₂ gas through the porous film and, atthe same time, forming a barrier film containing a compound of thepreset metal element, Si element and O element from the O₂ gas as a maincomponent in a self-alignment fashion on the surface of the alloy film.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a cross-sectional view showing a semiconductor deviceaccording to a first embodiment of this invention;

FIG. 2 is a view showing a microphotograph of a cross-sectional TEMimage of a portion near a barrier film of an aerial wiring;

FIG. 3 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the first embodiment of thisinvention;

FIG. 4 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the first embodiment of thisinvention;

FIG. 5 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the first embodiment of thisinvention;

FIG. 6 is a cross-sectional view showing one manufacturing step of asemiconductor device according to a modification 1 of this invention;

FIG. 7 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the modification 1 of this invention;FIG. 8 is a cross-sectional view showing a semiconductor deviceaccording to a second embodiment of this invention;

FIG. 9 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the second embodiment of thisinvention;

FIG. 10 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the second embodiment of thisinvention;

FIG. 11 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the second embodiment of thisinvention;

FIG. 12 is a cross-sectional view showing one manufacturing step of asemiconductor device according to a modification 2 of this invention;

FIG. 13 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the modification 2 of this invention;

FIG. 14 is a cross-sectional view showing one manufacturing step of asemiconductor device according to a modification 3 of this invention;

FIG. 15 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the modification 3 of this invention;and

FIG. 16 is a cross-sectional view showing one manufacturing step of thesemiconductor device according to the modification 3 of this invention.

DETAILED DESCRIPTION OF THE INVENTION

There will now be described embodiments of this invention with referenceto the accompanying drawings. In this explanation, common referencesymbols are attached to like portions throughout the drawings.

First Embodiment

First, a semiconductor device according to a first embodiment of thisinvention is explained with reference to FIGS. 1 and 2. FIG. 1 is across-sectional view showing the semiconductor device according to thepresent embodiment of this invention.

As shown in FIGS. 1 and 2, aerial wirings W1, W2 are provided in aninter-level insulating film 17 or air gap 15. The wirings W1, W2 are amultilayer wiring having substantially the same structures laminated ona semiconductor substrate such as a silicon substrate in practice.However, in this explanation, only part of the multilayer wiring isextracted and explained and the other portions thereof and theexplanation thereof are omitted.

The aerial wiring W1 includes a wiring layer 22-1 formed in the air gap15 and containing Cu as a main component (that is, 50 at % or more) anda via layer 23-1 electrically connected to the wiring layer 22-1, formedin the inter-level insulating film 17 and containing Cu as a maincomponent.

The aerial wiring W2 includes a wiring layer 22-2 formed in the air gap15 and containing Cu as a main component (that is, 50 at % or more). Inthe cross section, the via layer of the aerial wiring W2 is not shown.

In the air gap 15, a material used to isolate adjacent wirings from eachother is not a solid material represented by a silicon oxide film but agaseous material such as air, for example.

A porous film 11-2 is formed on the aerial wirings W1, W2. Specifically,the porous film 11-2 is formed of a porous Si film, for example.

The inter-level insulating film 17 is an SiOC film or the like which isone type of an inter-level insulating film with a small dielectricconstant (a so-called low-k film).

A porous film 11-1 is formed near the bottom portion of the aerialwiring W1. Specifically, the porous film 11-1 is formed of a porous Sifilm, for example.

Barrier films 25-1, 25-2 are formed to cover the surfaces of the aerialwirings W1, W2. Each of the barrier films 25-1, 25-2 contains a compoundof a preset constituent element (for example, Si, O) and a preset metalelement a (for example, Mn) as a main component and is formed in aself-alignment fashion. In this example, it is formed of anMn_(x)Si_(y)O_(z) (manganese silicon oxide) film. The composition of theMn_(x)Si_(y)O_(z) film is specifically expressed by 1:1:3 to 1:3:5 asx:y:z of Mn_(x)Si_(y)O_(z). Further, the barrier films 25-1, 25-2function as barriers which prevent diffusion of Cu (copper) in thewiring layers 22-1, 22-2 and via layer 23-1.

In this case, the barrier films 25-1, 25-2 are more specificallyexplained with reference to FIG. 2. FIG. 2 is a view showing amicrophotograph of a cross-sectional TEM image of a portion near thebarrier film 25-1 of the aerial wiring W1. In this explanation, a casewherein the barrier film 25-1 is used as an example is explained.

As shown in FIG. 2, the barrier film 25-1 is a thin and uniform Mn_(x)Si_(y)O_(z) film and the film thickness D1 is approximately 2 to 3 nm.

The preset metal element a is not limited to Mn as in the presentembodiment and may be an element selected from a group consisting of Nb,Zr, Cr, V, Y, Tc and Re. Each of the above metal elements a is a metalelement which has diffusion speed higher than Cu in a layer containingCu and tends to more easily react with oxygen than Cu to form athermally stabilized oxide.

The preset constituent element can contain O and at least one elementselected from a group consisting of Si, C and F. As a specific material,for example, SiO₂, SiO_(x)C_(y), SiO_(x)C_(y)H_(z), SiO_(x)F_(y) and thelike can be provided.

Further, the barrier film 25-1 can contain a material selected from agroup consisting of α_(x)O_(y), α_(x)Si_(y)O_(z), α_(x)C_(y)O_(z) andα_(x)F_(y)O_(z) as a main component. In this case, α indicates thepreset metal element α.

Thus, since the barrier film (Mn_(x)Si_(y)O_(z) film) 25-1 is an oxidefilm, it is not oxidized any more. Therefore, the oxidation resistanceof the aerial wirings W1, W2 can be enhanced and the aerial wirings W1,W2 can be protected from being oxidized.

Further, since a continuous and fine reaction-formed film which is nomore oxidized is attained, it prevents water from being passedtherethrough. Therefore, the water resistance of the wiring layers W1,W2 can be enhanced.

<Manufacturing Method>

Next, a manufacturing method of the semiconductor device is explainedwith reference to FIGS. 3 to 5 by taking the semiconductor device shownin FIGS. 1 and 2 as an example. In this explanation, the manufacturingprocesses for forming element isolation regions and metal oxidesemiconductor field effect transistors (MOSFETs) are omitted in thedrawing.

First, an element structure such as a MOSFET structure is formed on asemiconductor substrate by use of a known manufacturing process. Then,SiOC or the like is deposited to cover the element structure and form aninter-level insulating film (not shown) by use of a chemical vapordeposition (CVD) method, for example.

Next, as shown in FIG. 3, a porous Si film containing at least Si(silicon) in the composition thereof is deposited to form a porous film11-1 on the inter-level insulating film by use of the CVD method. Then,for example, an SiOC film or the like is deposited on the porous film11-1 to form an inter-level insulating film 17 by use of the CVD method.Further, an SiC film, SiCN film or the like is deposited to form anetching stopper film 12 on the inter-level insulating film 17 by use ofthe CVD method, for example.

Then, an Si-series resist film is deposited to form an insulating film30 by use of the CVD method, for example. In this case, the insulatingfilm 30 is not limited to the Si-series resist film and a material whichcan be eliminated by an etching process in a gaseous atmospherecontaining at least O₂ and contains at least Si in the compositionthereof can be used. For example, a sealing film having an Si containingthin insulating film formed to cover a portion of a resist film havingSi doped therein by silicifying, a polyarylene ether film having Sidoped therein by silicifying, or a resist film or polyarylene ether filmwhich faces the grooves for the wirings can be used.

Next, photoresist is coated on the insulating film 30 and the thusformed photoresist film is subjected to the exposing and developingprocesses. Thus, the patterning process is performed to expose thesurface of a portion of the insulating film 30 which corresponds inposition to the via layer 23-1. Further, an anisotropic etching processsuch as a reactive ion etching (RIE) process is performed to etch thestructure to the surface of the etching stopper film 12 with the thuspatterned photoresist film used as a mask (not shown).

Then, after the photoresist film is removed by ashing or the like,photoresist is further coated on the insulating film 30 and the thusformed photoresist film is subjected to the exposing and developingprocesses. Thus, the patterning process is performed to expose thesurface of portions of the insulating film 30 which correspond inposition to the wiring layers 22-1, 22-2. Further, an anisotropicetching process such as an RIE process is performed to etch thestructure to the surface of the inter-level insulating film 17 so as toform grooves 31, 32 for wirings with the thus patterned photoresist filmused as a mask.

Next, CuMn alloy layers 33-1, 33-2 are formed on the inner walls of thegrooves 31, 32 for wirings by use of a physical vapor deposition (PVD)method or CVD method, for example. After this, CuMn alloy layers 35-1,35-2 are formed on the CuMn alloy layers 33-1, 33-2 by use of a platingmethod, for example. Further, the CuMn alloy layers 33-1, 33-2, 35-1,35-2 are polished to the surface of the insulating film 30 and made flatby use of a chemical mechanical polishing method (CMP). Then, a porousSi film or the like is deposited to form a porous insulating film 11-2on the thus flattened CuMn alloy layers 33-1, 33-2, 35-1, 35-2 andinsulating film 30 by use of the CVD method. In this case, it isrequired for the porous film 11-2 to contain at least Si in thecomposition.

Next, as shown in FIG. 5, an etching process is performed through theporous film 11-2 in a gaseous atmosphere 36 containing O₂ to remove aportion of the insulating film 30 between the wirings and form an airgap 15.

In this case, at the time of the above etching process, the heattreatment is performed for 30 to 60 min to set the substrate temperatureat 200 to 600° C. By the heat treatment, Mn elements in the CuMn alloylayers 33-1, 33-2, 35-1, 35-2 are diffused to react with Si elements inthe insulating film 30, inter-level insulating film 17 and porous films11-1, 11-2 and O elements in the etching gas 36 to form uniformMn_(x)Si_(y)O_(z) films (barrier films) 25-1, 25-2 with extremely smallfilm thickness (2 to 3 nm) in a self-alignment fashion so as to coverthe surfaces thereof.

It is possible to precipitate almost all of the Mn elements in the CuMnalloy layers 35-1, 35-2 by suitably selecting the concentration of theMn elements and the reaction condition of the heat treatment process. Inthis case, the wiring layers 22-1, 22-2 and via layer 23-1 can be formedof pure Cu.

Further, by repeatedly performing the above manufacturing process, amultilayer wiring structure having an air gap structure with a desirednumber of layers can be formed. By the above manufacturing method, thesemiconductor device shown in FIGS. 1 and 2 is manufactured.

As described above, according to the semiconductor device and themanufacturing method of this embodiment, the following effects (1) to(5) can be attained.

(1) The oxidation resistance of the aerial wirings W1, W2 can beenhanced and oxidation and corrosion of the aerial wirings W1, W2 can beprevented to enhance the reliability.

Since the barrier films (Mn_(x)Si_(y)O_(z) films) 25-1, 25-2 are oxidefilms, they cannot be oxidized any more. Therefore, the barrier films25-1, 25-2 can be prevented from being oxidized and corroded byoxidation gas in the etching gas 36 in the etching process so that thewiring layers 22-1, 22-2 and via layer 23-1 contained therein can beprevented from being oxidized and corroded.

Further, since the barrier films 25-1, 25-2 can prevent penetration ofoxidation gas generated in the oxidation atmosphere at the LSI operationtime even after the aerial wirings W1, W2 are temporarily formed,oxidation and corrosion of the aerial wirings W1, W2 can be prevented.

Thus, the reliability of the aerial wirings W1, W2 can be enhanced.

(2) The water resistance of the aerial wirings W1, W2 can be enhanced.

Since the barrier films 25-1, 25-2 are each formed of a continuous andfine reaction-formed film, they prevent water from being passedtherethrough. Particularly, the inter-level insulating film 17 is formedof an SiOC film or the like which is one type of an inter-levelinsulating film (a low-k film) with small dielectric constant, but theSiOC film with the small dielectric constant generally has a propertythat it will easily pass water in addition to the property that it tendsto contain a large amount of water. However, since the barrier film 25-1is formed on the surface of the via layer 23-1, penetration of water canbe prevented.

Therefore, the water resistance of the wiring layers W1, W2 can beenhanced.

(3) The mechanical strength of the aerial wirings W1, W2 is high.

The air gap 15 is provided only between the wiring layers 22-1 and 22-2and the inter-level insulating film 17 which is a solid body is filledbetween the via layers 23-1. Therefore, occurrence of cracks in theaerial wirings W1, W2 can be prevented and the mechanical strengththereof becomes high.

(4) The capacitance between the wirings can be reduced and the delaytime caused by the aerial wirings W1, W2 can be reduced.

The wiring layers 22-1, 22-2 are provided in the air gap 15. In the airgap 15, for example, gas such as air is filled and the relativedielectric constant of air is smaller than that of a solid material suchas an insulating material and is set to approximately 1.0. Further, itis known that the capacitance between the wirings increases with anincrease in the relative dielectric constant of a portion between thewirings.

Therefore, the capacitances of the wiring layers 22-1, 22-2 in the airgap 15 can be reduced and the delay time in the aerial wirings W1, W2can be reduced.

(5) It is advantageous in reducing the manufacturing cost.

As described above, the etching process and the heat treatment aresimultaneously performed, the insulating film 30 is removed by use ofthe etching gas 36 in the etching process to form the air gap 15 and, atthe same time, O elements required for forming the barrier films 25-1,25-2 can be supplied. Therefore, the air gap 15 and the barrier films25-1, 25-2 can be simultaneously formed.

Thus, since the number of manufacturing steps is reduced to simply themanufacturing process, it is advantageous in reducing the manufacturingcost.

Modification 1 Example of Formation of Air Gap after Formation ofBarrier Film

Next, a manufacturing method of a semiconductor device according to amodification 1 of this invention is explained with reference to FIGS. 6and 7. The manufacturing method of the semiconductor device according tothe modification 1 relates to a case wherein an air gap is formed aftera barrier film is first formed. In this explanation, the explanation forportions which have been explained in the first embodiment is omitted.

Since the configuration of the semiconductor device according to themodification 1 is the same as that of the semiconductor device accordingto the first embodiment shown in FIGS. 1 and 2, the explanation thereofis omitted.

<Manufacturing Method>

First, an element structure such as a MOSFET structure is formed on asemiconductor substrate by use of a known manufacturing method. Then,SiOC or the like is deposited to cover the element structure and form aninter-level insulating film (not shown) by use of the CVD method, forexample.

Next, as shown in FIG. 6, a porous film 11-1, inter-level insulatingfilm 17, etching stopper film 12 and insulating film 30 are sequentiallyformed on the inter-level insulating film by use of the samemanufacturing method as that of the first embodiment. After this,grooves for wirings are formed in the laminated film.

Then, CuMn alloy layers are formed on the inner walls of the grooves forwirings by use of the PVD or CVD method, for example. After this, CuMnalloy layers 35-1, 35-2 are formed on the CuMn alloy layers by use ofthe plating method, for example. The CuMn alloy layers 35-1, 35-2 arepolished to the surface of the insulating film 30 and made flat by useof the CMP method and a porous film 11-2 is formed on the thus flattenedCuMn alloy layers 35-1, 35-2 and insulating film 30.

Next, the heat treatment is performed for 30 to 60 min to set thesubstrate temperature at 200 to 600° C. By the heat treatment, Mnelements in the CuMn alloy layers 35-1, 35-2 are diffused to react withO elements and Si elements in the insulating film 30, inter-levelinsulating film 17 and porous films 11-1, 11-2 to form uniformMn_(x)Si_(y)O_(z) films (barrier films) 25-1, 25-2 with extremely smallfilm thickness (2 to 3 nm) in a self-alignment fashion so as to coverthe surfaces thereof.

It is possible to precipitate almost all of the Mn elements in the CuMnalloy layers 35-1, 35-2 by suitably selecting the concentration of theMn elements and the reaction condition of the heat treatment process. Inthis case, the wiring layers 22-1, 22-2 and via layer 23-1 can be formedof pure Cu.

Then, as shown in FIG. 7, an etching process is performed through theporous film 11-2 in a gaseous atmosphere containing O₂ to removeportions of the insulating film 30 which lie between the wirings andform an air gap 15.

Further, by repeatedly performing the above manufacturing process, amultilayer wiring structure having an air gap structure with a desirednumber of layers can be formed. By the above manufacturing method, thesemiconductor device shown in FIGS. 1 and 2 is manufactured.

As described above, according to the semiconductor device and themanufacturing method of this embodiment, the same effects as effects (1)to (5) can be attained.

Further, in the manufacturing method of the semiconductor deviceaccording to the modification 1, the insulating film 30 is selectivelyremoved by performing the etching process to form the air gap 15 afterthe barrier films 25-1, 25-2 are formed by the heat treatment process.

Thus, the manufacturing steps of forming the barrier films 25-1, 25-2and forming the air gap 15 can be independently performed. Therefore,the manufacturing steps can be performed with the optimum gas conditionand temperature condition adequately set in the respective manufacturingsteps. As a result, the film quality of the barrier films 25-1, 25-2 canbe further enhanced and the quality of gas which occupies the air gap 15can be enhanced.

Second Embodiment Example in which Wiring Layers and Via Layers areprovided in Air Gap

Next, a semiconductor device according to a second embodiment of thisinvention is explained with reference to FIG. 8. The semiconductordevice according to the second embodiment relates to a case whereinwiring layers and via layers are formed in an air gap. In thisexplanation, the explanation for portions which have been explained inthe first embodiment is omitted.

As shown in FIG. 8, the present embodiment is different from the firstembodiment in that an etching stopper film is not formed and wiringlayers 22-1, 22-2 and via layer 23-1 of aerial wirings W3, W4 are formedin an air gap 40.

That is, the aerial wiring W3 includes the wiring layer 22-1 formed inthe air gap 40 and containing Cu as a main component and the via layer23-1 electrically connected to the wiring layer 22-1, formed in the airgap 40 and containing Cu as a main component.

The aerial wiring W4 includes the wiring layer 22-2 formed in the airgap 40 and containing Cu as a main component. In the cross section, avia layer of the aerial wiring W4 is not shown.

<Manufacturing Method>

Next, a manufacturing method of the semiconductor device according tothe present embodiment is explained with reference to FIGS. 9 to 11 bytaking the semiconductor device shown in FIG. 8 as an example. In thisexplanation, the process for manufacturing element isolation regions andMOSFETs is not shown in the drawing.

First, an element structure such as a MOSFET structure is formed on asemiconductor substrate by use of a known manufacturing method. Then,SiOC or the like is deposited to cover the element structure and form aninter-level insulating film (not shown) by use of the CVD method, forexample.

After this, as shown in FIG. 9, a porous Si film containing at least Siin the composition is deposited to form a porous film 11-1 on theinter-level insulating film by use of the CVD method, for example.

Next, an Si-series resist film is deposited on the porous film 11-1 toform an insulating film 30 by use of the CVD method, for example. Theinsulating film 30 is not limited to the Si-series resist film. Forexample, a material which can be removed by an etching process using agaseous atmosphere containing at least O₂ and contains at least Si inthe composition can be applied. For example, a sealing film having an Sicontaining thin insulating film formed to cover a portion of a resistfilm having Si doped therein by silicifying, a polyarylene ether filmhaving Si doped therein by silicifying, or a resist film or polyaryleneether film which faces the groove for the wiring can be used.

Then, grooves 41, 42 for wirings are formed by use of the manufacturingmethod which is substantially the same as that of the first embodiment.

Next, as shown in FIG. 10, CuMn alloy layers 33-1, 33-2 are formed onthe inner walls of the grooves 41, 42 for wirings by use of the PVDmethod or CVD method, for example. After this, CuMn alloy layers 35-1,35-2 are formed on the CuMn alloy layers 33-1, 33-2 by use of theplating method, for example. The CuMn alloy layers 33-1, 33-2, 35-1,35-2 are polished to the surface of the insulating film 30 and made flatby use of the CMP method. Then, a porous insulating film 11-2 is formedby depositing a porous Si film or the like on the thus flattened CuMnalloy layers 33-1, 33-2, 35-1, 35-2 and insulating film 30. The porousfilm 11-2 is required to contain at least Si in the composition.

Next, as shown in FIG. 11, an etching process is performed through theporous film 11-2 in a gaseous atmosphere 36 containing O₂ to removeportions of the insulating film 30 which lie between the wirings andform an air gap 40.

At the time of the above etching process, the heat treatment isperformed for 30 to 60 min to set the substrate temperature at 200 to600° C. By the heat treatment, Mn elements in the CuMn alloy layers33-1, 33-2, 35-1, 35-2 are diffused to react with Si elements in theinsulating film 30 and porous films 11-1, 11-2 and O elements in theetching gas to form uniform Mn_(x)Si_(y)O_(z) films (barrier films)25-1, 25-2 with extremely small film thickness (2 to 3 nm) in aself-alignment fashion so as to cover the surfaces thereof.

It is possible to precipitate almost all of the Mn elements in the CuMnalloy layers 35-1, 35-2 by suitably selecting the concentration of theMn elements and the reaction condition of the heat treatment process. Inthis case, the wiring layers 22-1, 22-2 and via layer 23-1 can be formedof pure Cu.

Further, by repeatedly performing the above manufacturing process, amultilayer wiring structure having an air gap structure with a desirednumber of layers can be formed. By the above manufacturing method, thesemiconductor device shown in FIG. 8 is manufactured.

As described above, according to the semiconductor device and themanufacturing method of this embodiment, the same effects as effects(1), (2), (4) and (5) can be attained.

Further, in the semiconductor device according to the presentembodiment, the wiring layers 22-1, 22-2 and the via layer 23-1 areformed in the air gap 40.

Therefore, by reducing the relative dielectric constant of a portionbetween the wirings, an advantage that the capacitance can be reducedand the delay time of the aerial wirings W1, W2 can be reduced can beattained.

In the present embodiment, an etching stopper film (middle stopper film)is not used between the wiring-wiring insulating film and the via-viainsulating film, but in the structure in which the etching stopper filmis used, the same effect can be attained.

Modification 2 Example of Formation of Air Gap after Formation ofBarrier Film

Next, a manufacturing method of a semiconductor device according to amodification 2 of this invention is explained with reference to FIGS.12, 13. The manufacturing method of the semiconductor device accordingto the modification 2relates to a case wherein an air gap is formedafter a barrier film is first formed. In this explanation, theexplanation for portions which have been explained in the secondembodiment is omitted.

<Manufacturing Method>

First, an element structure such as a MOSFET structure is formed on asemiconductor substrate by use of a known manufacturing method. Then,SiOC or the like is deposited to cover the element structure and form aninter-level insulating film (not shown) by use of the CVD method, forexample.

Next, as shown in FIG. 12, a porous film 11-1 and insulating film 30 aresequentially formed on the inter-level insulating film by use of thesame manufacturing method as that of the second embodiment and groovesfor wirings are formed in the laminated film.

Then, CuMn alloy layers are formed on the inner walls of the grooves forwirings by use of the PVD method or CVD method, for example. After this,CuMn alloy layers 35-1, 35-2 are formed on the CuMn alloy layers by useof the plating method, for example. The CuMn alloy layers 35-1, 35-2 arepolished to the surface of the insulating film 30 and made flat by useof the CMP method and a porous film 11-2 is formed on the thus flattenedCuMn alloy layers 35-1, 35-2.

Next, the heat treatment is performed for 30 min to 60 min to set thesubstrate temperature at 200 to 600° C. By the heat treatment, Mnelements in the CuMn alloy layers 35-1, 35-2 are diffused to react withO elements and Si elements in the insulating film 30 and porous films11-1, 11-2 to form uniform Mn_(x)Si_(y)O_(z) films (barrier films) 25-1,25-2 with extremely small film thickness (2 to 3 nm) in a self-alignmentfashion so as to cover the surfaces thereof.

It is possible to precipitate almost all of the Mn elements in the CuMnalloy layers 35-1, 35-2 by suitably selecting the concentration of theMn elements and the reaction condition of the heat treatment process. Inthis case, the wiring layers 22-1, 22-2 and via layer 23-1 can be formedof pure Cu.

Then, as shown in FIG. 13, an etching process is performed through theporous film 11-2 in a gaseous atmosphere 36 containing O₂ to removeportions of the insulating film 30 which lie between the wirings andform an air gap 40.

Further, by repeatedly performing the above manufacturing process, amultilayer wiring structure having an air gap structure with a desirednumber of layers can be formed. By the above manufacturing method, thesemiconductor device shown in FIG. 8 is manufactured.

As described above, according to the semiconductor device and themanufacturing method of this embodiment, the same effects as effects(1), (2), (4) and (5) can be attained.

Further, in the manufacturing method of the semiconductor deviceaccording to the modification 2, the barrier films 25-1, 25-2 are firstformed by the heat treatment process and the air gap 40 is formed by theetching process.

Thus, the manufacturing steps of forming the barrier films 25-1, 25-2and forming the air gap 40 can be independently performed. Therefore,the manufacturing steps can be performed with the optimum gas conditionand temperature condition adequately set in the respective manufacturingsteps. As a result, an advantage that the film quality of the barrierfilms 25-1, 25-2 can be further enhanced and the quality of gas in theair gap 40 can be enhanced can be attained.

Modification 3

Next, a the manufacturing method of a semiconductor device according toa modification 3 is explained with reference to FIGS. 14 to 16. In thisexplanation, the explanation for portions which have been explained inthe second embodiment is omitted.

Since the structure of the semiconductor device according to themodification 3 is the same as that of the semiconductor device accordingto the second embodiment, the detail explanation thereof is omitted.

<Manufacturing Method>

First, an element structure such as a MOSFET structure is formed on asemiconductor substrate by use of a known manufacturing process. Then,SiOC or the like is deposited to cover the element structure and form aninter-level insulating film (not shown) by use of the CVD method, forexample.

Next, as shown in FIG. 14, a porous film 11-1 is formed on theinter-level insulating film by use of the same manufacturing method asthat used in the second embodiment.

Then, an insulating film 57 which contains no Si is formed on the porousfilm 11-1 by use of the CVD method, for example. The insulating film 57which contains no Si is a resist film containing no Si, polyaryleneether film or the like.

After this, grooves 41, 42 for wirings are formed in the insulating film57 by use of the same manufacturing process as that used in the secondembodiment.

Next, thin insulating films 55-1, 55-2 containing Si are formed on theinner walls of the grooves 41, 42 for wirings by use of the CVD method,for example. The insulating films 55-1, 55-2 containing Si are an SiO₂film, SiF film, SiOC film, SiC film, SiCN film, SiN film or the like,for example.

Further, CuMn alloy layers acting as seed layers are formed on theinsulating films 55-1, 55-2 by use of the PVD method or CVD method, forexample (not shown).

Then, as shown in FIG. 15, CuMn alloy layers 35-1, 35-2 are formed onthe CuMn alloy layers by use of the plating method, for example.Further, the CuMn alloy layers 35-1, 35-2 are polished to the surface ofthe insulating film 57 and made flat by use of the CMP method. Afterthis, a porous film 11-2 is formed on the thus flattened CuMn alloylayers 35-1, 35-2. In this case, the CuMn alloy layers acting as theseed layers are integrated with the respective CuMn alloy layers 35-1,35-2 in some cases.

Next, as shown in FIG. 16, an etching process is performed through theporous film 11-2 in a gaseous atmosphere 36 containing O₂ to remove aportion of the insulating film 57 which lies between the wirings andform an air gap 40.

In this case, at the time of the above etching process, the heattreatment is performed for 30 min to 60 min to set the substratetemperature at 200° C. to 600° C. By the heat treatment, Mn elements inthe CuMn alloy layers 35-1, 35-2 are diffused to react with Si elementsin the insulating films 55-1, 55-2 and porous films 11-1, 11-2 and Oelements in the etching gas 36 to form uniform Mn_(x)Si_(y)O_(z) films(barrier films) 25-1, 25-2 with extremely small film thickness (2 nm to3 nm) in a self-alignment fashion so as to cover the surfaces thereof.

It is possible to precipitate almost all of the Mn elements in the CuMnalloy layers 35-1, 35-2 by suitably selecting the concentration of theMn elements and the reaction condition of the heat treatment process. Inthis case, the wiring layers 22-1, 22-2 and via layer 23-1 can be formedof pure Cu.

Further, by repeatedly performing the above manufacturing process, amultilayer wiring structure having an air gap structure with a desirednumber of layers can be formed. By the above manufacturing method, thesemiconductor device shown in FIG. 8 is manufactured.

As described above, according to the semiconductor device and themanufacturing method of this embodiment, the same effects as the effects(1), (2), (4) and (5) can be attained.

Further, in the manufacturing method of the semiconductor deviceaccording to the modification 3, the insulating films 55-1, 55-2containing Si are formed on the inner walls of the grooves 41, 42. The Oelements required for forming the barrier films 25-1, 25-2 are suppliedfrom the etching gas 36 used in the etching process. On the other hand,the Mn elements are supplied by diffusing Mn elements from the CuMnalloy layers 35-1, 35-2 to the peripheral regions in the heat treatmentprocess which is performed at the same time as the above etchingprocess.

Therefore, the insulating film 57 removed at the time of the etchingprocess can be formed of an insulating film which contains no Si sinceit is not necessary for the insulating film to supply elements requiredfor forming the barrier films 25-1, 25-2. Thus, it is advantageous inwidening the selection range of insulating materials for the insulatingfilm 57 to be etched.

One example of the insulating films 55-1, 55-2, 57 is explained bytaking a case wherein the wiring layers and via layers according to thesecond embodiment and modification 2 are formed in the air gap as anexample. However, the insulating films 55-1, 55-2, 57 can also beapplied to a case wherein the wiring layers according to the firstembodiment and modification 1 are formed in the air gap.

Further, in the wiring structure shown in the first embodiment andmodification 1, the types of the insulating films for the wiring layersand via layers are different, but the two insulating films can be formedof the same type. In addition, the wiring groove is formed in a dualdamascene form, but the same effect can be attained even if it is formedin a single damascene form.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-15. (canceled)
 16. A method of manufacturing a semiconductor devicecomprising: forming a groove for wiring in an insulating film above asubstrate; embedding an alloy film including a preset metal element andcontaining Cu as a main component into the groove; forming a porous filmcontaining at least Si on the alloy film and insulating film; andforming an air gap by removing a portion of the insulating film byperforming heat treatment together with an etching process through theporous film in an atmosphere containing at least O₂ gas and, at the sametime, forming a barrier film containing a compound of the preset metalelement, Si element and O element from the O₂ gas as a main component ina self-alignment fashion on the surface of the alloy film.
 17. Themethod of manufacturing a semiconductor device according to claim 16,wherein the insulating film contains at least Si.
 18. The method ofmanufacturing a semiconductor device according to claim 16, wherein thepreset metal element includes at least one element selected from thegroup consisting of Mn, Nb, Zr, Cr, V, Y, Tc and Re.
 19. The method ofmanufacturing a semiconductor device according to claim 16, in which theinsulating film is an insulating film which contains no Si, and whichfurther comprises forming an insulating film containing Si on an innerwall of the groove before the alloy film is embedded.
 20. The method ofmanufacturing a semiconductor device according to claim 19, wherein theinsulating film which contains no Si includes at least one of apolyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises at least one of an SiO₂film, SiOF film, SiOC film, SiC film, SiCN film and SiN film.
 21. Themethod of manufacturing a semiconductor device according to claim 19,wherein the insulating film which contains no Si includes at least oneof a polyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises a SiO₂ film.
 22. The methodof manufacturing a semiconductor device according to claim 19, whereinthe insulating film which contains no Si includes at least one of apolyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises a SiOF film.
 23. The methodof manufacturing a semiconductor device according to claim 19, whereinthe insulating film which contains no Si includes at least one of apolyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises a SiOC film.
 24. The methodof manufacturing a semiconductor device according to claim 19, whereinthe insulating film which contains no Si includes at least one of apolyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises a SiC film.
 25. The methodof manufacturing a semiconductor device according to claim 19, whereinthe insulating film which contains no Si includes at least one of apolyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises a SiCN film.
 26. The methodof manufacturing a semiconductor device according to claim 19, whereinthe insulating film which contains no Si includes at least one of apolyarylene ether film and a resist film containing no Si and theinsulating film which contains Si comprises a SiN film.
 27. The methodof manufacturing a semiconductor device according to claim 16, whereinthe alloy of said alloy film is a CuMn alloy.
 28. The method ofmanufacturing a semiconductor device according to claim 16, wherein saidheat treatment is performed for 30 to 60 minutes to set the substratetemperature at 200 to 600° C.